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this product conforms to the specifications per the terms of the ramtron standard warranty. ramtron international corporation the product has completed ramtron?s intern al qualification testing and has reached 1850 ramtron drive, colorado springs, co 809 21 production status. (800) 545-fram, (719) 481-7000 http://www.ramtron.com rev. 2.0 june 2012 page 1 of 13 fm23mld16 8mbit f-ram memory features 8mbit ferroelectric nonvolatile ram ? organized as 512kx16 ? configurable as 1mx8 using /ub, /lb ? high endurance 100 trillion (10 14 ) read/writes ? nodelay? writes ? page mode operation to 33mhz ? advanced high-reliability ferroelectric process sram compatible ? jedec 512kx16 sram pinout ? 60 ns access time, 115 ns cycle time advanced features ? low v dd monitor protects memory against inadvertent writes superior to battery-backed sram modules ? no battery concerns ? monolithic reliability ? true surface moun t solution, no rework steps ? superior for moisture, shock, and vibration low power operation ? 2.7v ? 3.6v power supply ? 14 ma active current industry standard configuration ? industrial temperature -40 c to +85 c ? 48-pin ?green?/rohs fbga package description the fm23mld16 is a 512kx16 nonvolatile memory that reads and writes like a standard sram. a ferroelectric random access memory or f-ram is nonvolatile, which means that data is retained after power is removed. it provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed sram (bbsram). fast write timing and very high write endurance make f-ram superior to other types of memory. in-system operation of the fm23mld16 is very similar to other ram devices and can be used as a drop-in replacement for standard sram. read and write cycles may be triggered by a chip enable or simply by changing th e address. the f-ram memory is nonvolatile due to its unique ferroelectric memory process. these features make the fm23mld16 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an sram. the fm23mld16 includes a low voltage monitor that blocks access to the memory array when v dd drops below a critical threshold. the memory is protected against an inadvertent access and data corruption under this condition. the fm23mld16 f-ram is available in a 48-ball fbga surface mount package. device specifications are guaranteed over the industrial temperature range of ?40c to +85c. 48-ball fbga top view (ball down) /lb /oe a0 a1 a2 ce2 dq8 /ub a3 a4 /ce1 dq0 dq9 dq10 a5 a6 dq1 dq2 vss dq11 a17 a7 dq3 vdd vdd dq12 nc a16 dq4 vss dq14 dq13 a14 a15 dq5 dq6 dq15 nc a12 a13 /we dq7 a18a8 a9a10a11nc 123456 a b c d e f g h ordering information FM23MLD16-60-BG 60 ns access, 48-pin ?green?/rohs fbga
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 2 of 13 64k x 64 address latch control logic we chip & row decoder a(18:2) a(1:0) i/o latch & bus driver oe dq(15:0) 64k x 64 f-ram array a(18:0) column decoder ub, lb 2 ce1, ce2 2 figure 1. block diagram pin description pin name type pin description a(18:0) input address inputs: the a( 17:0) address lines select one of 262,144 words in each of the f- ram die. a18 selects one of the two die. the lowest two address lines a(1:0) may be used for page mode read and write operations. /ce1, ce2 input chip enab le inputs: the device is selected and a new memory access begins on the falling edge of /ce1 (while ce2 high) or the rising edge of ce2 (while /ce1 low). the entire address is latched internally at this point. /we input write enable: a write cycle begins when /we is asserted. the rising edge causes the fm23mld16 to write the data on the dq bus to the f-ram array. the falling edge of /we latches a new column address for page mode write cycles. /oe input output enable: when /oe is low, the fm23mld16 drives the data bus when valid read data is available. deasserting /oe high tri-states the dq pins. dq(15:0) i/o data: 16-bit bi-directional data bus for accessing the f-ram array. /ub input upper byte select: enables dq(15:8) pins during reads and writes. these pins are hi-z if /ub is high. /lb input lower byte select: enables dq(7:0) pins during reads and writes. these pins are hi-z if /lb is high. vdd supply supply voltage: 3.3v vss supply ground
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 3 of 13 functional truth table 1 /ce1 ce2 /we a(18:2) a(1:0) operation h x x l x x x x x x standby/idle l h h h v v v v read l h h no change change page mode read l h h change v random read l h l l v v v v /ce-controlled write 2 l h v v /we-controlled write 2, 3 l h no change v page mode write 4 l h x x x x x x starts precharge notes: 1) h=logic high, l=logic low, v=valid data, x=don?t care. 2) for write cycles, data-in is latc hed on the rising edge of /ce1 or /we of the falling edge of ce2, whichever comes first. 3) /we-controlled write cycle begins as a read cycle and a(18:3) is latched then. 4) addresses a(2:0) must remain stable for at least 15 ns during pa ge mode operation. byte select truth table /oe /lb /ub operation h x x read; outputs disabled x h h l h l read; dq(7:0) hi-z l h read; dq(15:8) hi-z l l read x h l write; mask dq(7:0) l h write; mask dq(15:8) l l write
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 4 of 13 overview the fm23mld16 is a wordwide f-ram memory logically organized as 524,288 x 16 and accessed using an industry standard parallel interface. all data written to the part is immediately nonvolatile with no delay. the device offers page mode operation which provides higher speed acces s to addresses within a page (row). an access to a different page is triggered by toggling a chip enable pin or simply by changing the upper address a(18:2). memory operation users access 524,288 memory locations, each with 16 data bits through a parallel interface. the f-ram memory is organized as 2 die each having 64k rows. each row has 4 column locations, which allows fast access in page mode operation. once an initial address has been latched by the falling edge of /ce1 (while ce2 high) or the rising edge of ce2 (while /ce1 low), subsequent column locations may be accessed without the need to toggle a chip enable. when either chip enable pin is deasserted, a precharge operation begins. writes occur immediately at the end of the access with no delay. the /we pin must be toggled for each write operation. the write data is stored in the nonvolatile memory array immediately, which is a feature unique to f-ram called nodelay tm writes. read operation a read operation begins on the falling edge of /ce1 (while ce2 high) or the rising edge of ce2 (while /ce1 low). the /ce-initiated access causes the address to be latched and starts a memory read cycle if /we is high. data becomes available on the bus after the access time has been satisfied. once the address has been latched and the access completed, a new access to a random location (different row) may begin while both chip enables are still active. the minimum cycle time for random addresses is t rc . note that unlike srams, the fm23mld16?s /ce- initiated access time is faster than the address cycle time. the fm23mld16 will drive the data bus when /oe and at least one of the byte enables (/ub, /lb) is asserted low. the upper data byte is driven when /ub is low, and the lower data byte is driven when /lb is low. if /oe is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. if /oe is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. this feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. when /oe is deasserted high, the data bus will remain in a high-z state. write operation writes occur in the fm23mld16 in the same time interval as reads. the fm23mld16 supports both /ce- and /we-controlled write cycles. in both cases, the address a(18:2) is latched on the falling edge of /ce1 (while ce2 high) or the rising edge of ce2 (while /ce1 low). in a /ce-controlled write, the /we signal is asserted prior to beginning the memory cycle. that is, /we is low when the device is activ ated with a chip enable. in this case, the device begins the memory cycle as a write. the fm23mld16 will not drive the data bus regardless of the state of /oe as long as /we is low. input data must be valid when the device is deselected with a chip enable. in a /we-controlled write, the memory cycle begins when the device is activated with a chip enable. the /we signal falls some time later. therefore, the memory cycle begins as a read. the data bus will be driven if /oe is low, however it will hi-z once /we is asserted low. the /ce- and /we-controlled write timing cases are shown in the electrical specifi cations section. in the write cycle timing 2 diagram, the data bus is shown as a hi-z condition while the chip is write-enabled and before the required setup time. although this is drawn to look like a mid-level voltage, it is recommended that all dq pins comply with the minimum v ih /v il operating levels. write access to the array begins on the falling edge of /we after the memory cycle is initiated. the write access terminates on the deassertion of /we, /ce1, or ce2, whichever comes first. a valid write operation requires the user to meet the access time specification prior to deasserting /we, /ce1, or ce2. data setup time indicates the interval during which data cannot change prior to the end of the write access (rising edge of /we or the chip is deselected with /ce1 or ce2). unlike other truly nonvola tile memory technologies, there is no write delay w ith f-ram. since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. data polling, a technique used with eeproms to determine if a write is complete, is unnecessary. page mode operation the fm23mld16 provides the user fast access to any data within a row el ement. each row has 4 column address locations. address inputs a(1:0) define the column address to be accessed. an access can start on any column address, and other column
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 5 of 13 locations may be accessed without the need to toggle the ce pins. for fast access reads, once the first data byte is driven onto the bus, the column address inputs a(1:0) may be changed to a new value. a new data byte is then driven to the dq pins no later than t aap , which is less than half th e initial read access time. for fast access writes, the first write pulse defines the first write access. while the device is selected (both chip enables asserted), a subsequent write pulse along with a new column address provides a page mode write access. precharge operation the precharge operation is an internal condition in which the state of the memory is being prepared for a new access. precharge is use r-initiated by driving at least one of the chip enable signals to an inactive state. it must remain high for at least the minimum precharge time t pc . sram drop-in replacement the fm23mld16 has been designed to be a drop-in replacement for standard asynchronous srams. the device does not require the ce pins to toggle for each new address. both ce pins may remain active indefinitely. when both ce pins are active, the device automatically detects address changes and a new access is begun. this functionality allows the chip enable pins to be tied active (/ce1 grounded, ce2 tied to v dd ) as you might with an sram. it also allows page mode operation at speeds up to 33mhz. a typical application is shown in figure 2. it shows a pullup resistor on /ce1 which will keep the pin high during power cycles assuming the mcu/mpu pin tri- states during the reset cond ition. the pullup resistor value should be chosen to ensure the /ce1 pin tracks v dd yet a high enough value that the current drawn when /ce1 is low is not an issue. although not required, it is recommended that ce2 be tied to v dd if the controller provides an active-low chip enable. figure 2. typical application using pullup resistor on /ce1 for applications that require the lowest power consumption, the /ce1 signal should be active only during memory accesses. the fm23mld16 draws supply current while /ce1 is low, even if addresses and control signals are static. while /ce1 is high, the device draws no more than the maximum standby current i sb . note that if /ce1 is grounded and ce2 tied to v dd , the user must be sure /we is not low at powerup or powerdown events. if the chip is enabled and /we is low during power cycles, data corruption will occur. figure 3 shows a pullup resistor on /we which will keep the pin high during power cycles assuming the mcu/mpu pin tri-states during the reset condition. the pullup resistor value should be chosen to ensure the /we pin tracks v dd yet a high enough value that the current drawn when /we is low is not an issue. a 10kohm resistor draws 330ua when /we is low and v dd =3.3v. figure 3. use of pullup resistor on /we the /ub and /lb byte select pins are active for both read and write cycles. they may be used to allow the device to be wired as a 1mx8 memory. the upper and lower data bytes can be tied together and controlled with the byte selects. individual byte enables or the next higher address line a(19) may be available from the system processor. figure 4. fm23mld16 wired as 1mx8 ce2 ce1 we oe a(18:0) dq(15:0) fm23mld16 v dd mcu/ mpu r ce2 ce1 we oe a(18:0) dq(15:0) fm23mld16 v dd mcu/ mpu r
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 6 of 13 pcb layout recommendations a 0.1uf decoupling capacito r should be placed close to each power/ground pair (solder balls 1d/1e and 6d/6e). the ground side of the capacitor should be connected to either a grou nd plane or low impedance path back to the v ss pins. it is best to use a chip capacitor that has low esr and has good high frequency characteristics. if the controller drives the address and chip enable from the same timing edge, it is best to keep the address routes short and of equal length. a simple rc circuit may be inserted in the chip enable path to provide some delay and timing margin for the fm23mld16?s address setup time t as . as a general rule, the layout designer may need to add series termination resistors to controller outputs that have fast transitions or routes that are > 15cm in length. this is only necessary if the edge rate is less than or equal to the round trip trace delay. signal overshoot and ringback may be large enough to cause erratic device behavior. it is best to add a 50 ohm resistor (30 ? 60 ohms) near the output driver (controller) to reduce such transmission line effects.
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 7 of 13 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss -1.0v to +4.5v v in voltage on any signal pin with respect to v ss -1.0v to +4.5v and v in < v dd +1v t stg storage temperature -55 c to +125 c t lead lead temperature (soldering, 10 seconds) 300 c v esd electrostatic discharge voltage - human body model (jedec std jesd22-a114-d) - charged device model (jedec std jesd22-c101-c) - machine model (jedec std jesd22-a115-a) 1.5kv 1.2kv 170v package moisture sensitivity level msl-3 stresses above those listed under absolute maximum ratings may cau se permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or an y other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ra tings conditions for extended periods may affect device reliabilit y. dc operating conditions (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min typ max units notes v dd power supply 2.7 3.3 3.6 v i dd power supply current 9 14 ma 1 i sb standby current @ t a = 25c @ t a = 85c 180 - 300 540 a a 2 v tp v dd trip point to block accesses 2.2 - 2.6 v 3 i li input leakage current 1 1 a) v dd -0.2 v v ol1 output low voltage ( i ol = 2.1 ma) 0.4 v v ol2 output low voltage ( i ol = 100 a) 0.2 v notes 1. v dd = 3.6v, ce pin(s) cycling at min. cycle time. all inputs toggling at cmos levels (0.2v or v dd -0.2v), all dq pins unloaded. 2. v dd = 3.6v, /ce1 at v dd or ce2 at v ss , all other pins are static an d at cmos levels (0.2v or v dd -0.2v). 3. if v dd < v tp , all memory accesses are blocked regardless of input pin conditions.
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 8 of 13 read cycle ac parameters (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min max units notes t rc read cycle time 115 - ns t ce chip enable access time - 60 ns t aa address access time - 115 ns t oh output hold time 25 - ns t aap page mode address access time - 28 ns t ohp page mode output hold time 5 - ns t ca chip enable active time 60 - ns t pc precharge time 55 - ns t ba /ub, /lb access time - 20 ns t as address setup time (to /ce1, ce2 active) 5 - ns t ah address hold time (ce-controlled) 60 - ns t oe output enable access time - 15 ns t hz chip enable to output high-z - 10 ns 1 t ohz output enable high to output high-z - 10 ns 1 t bhz /ub, /lb high to output high-z - 10 ns 1 write cycle ac parameters (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min max units notes t wc write cycle time 115 - ns t ca chip enable active time 60 - ns t cw chip enable to write enable high 60 - ns t pc precharge time 55 - ns t bhz /ub, /lb high to output high-z 5 ns t pwc page mode write enable cycle time 25 - ns t wp write enable pulse width 16 - ns t as address setup time (to /ce1, ce2 active) 5 - ns t asp page mode address setup time (to /we low) 8 - ns t ahp page mode address hold time (to /we low) 15 - ns t wlc write enable low to chip disabled 25 - ns t wla write enable low to a(18:2) change 25 - ns t awh a(18:2) change to write enable high 115 - ns t ds data input setup time 14 - ns t dh data input hold time 5 - ns t wz write enable low to output high z - 10 ns 1 t wx write enable high to output driven 10 - ns 1 t ws write enable to /ce low setup time 0 - ns 2 t wh write enable to /ce high hold time 0 - ns 2 notes 1 this parameter is guaranteed by design. 2 the relationship between /ce and /we determines if a /ce- or /we-controlled write occurs. the parameters t ws and t wh are not tested. capacitance (t a = 25 c , f=1 mhz, v dd = 3.3v) symbol parameter min max units notes c i/o input/output capacitance (all dq) - 16 pf c in1 input capacitance (/ce1, ce2, a18) - 6 pf c in2 input capacitance (a17-a0, /we, /oe, /lb, /ub) - 12 pf
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 9 of 13 power cycle timing (t a = -40 c to + 85 c, v dd = 2.7v to 3.6v unless otherwise specified) symbol parameter min max units notes t pu power-up to first access time (after v dd min) 450 - notes 1 slope measured at any point on v dd waveform. 2 ramtron cannot test or characterize all v dd power ramp profiles. the behavior of the internal circuits is difficult to predict when v dd is below the level of a transistor threshol d voltage. ramtron strongly recommends that v dd power up faster than 100ms through the range of 0.4v to 1.0v. data retention (v dd = 2.7v to 3.6v) parameter min units notes data retention @ +85c @ +80c @ +75c 5 10 20 years years years ac test conditions input pulse levels 0 to 3v input and output timing levels 1.5v input rise and fall times 3 ns output load capacitance 30pf read cycle timing 1 (/ce1 low, ce2 high, /oe low) read cycle timing 2 (/ce-controlled)
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 10 of 13 page mode read cycle timing 1. although sequential column addressing is shown, it is not required. write cycle timing 1 (/we-controlled, /oe low) d in ce1 a(18:0) we t ca t pc dq(15:0) t wp t cw t as d out d out t ds t dh t wx t wz t hz t wlc ce2 write cycle timing 2 (/ce-controlled)
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 11 of 13 write cycle timing 3 (/ce1 low, ce2 high) d in a(18:0) we dq(15:0) t wc t dh t wla t ds t awh d out d out t wz t wx d in page mode write cycle timing 1. although sequential column addressing is shown, it is not required.
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 12 of 13 mechanical drawing 48-ball fbga (0.75mm ball pitch) pin a1 6.00 bsc 1.20 max 0.10 mm 1.875 8.00 bsc 0.25 6.00 bsc 0.350.05 0.75 typ top view bottom view a b c d e f g h 6 5 4 3 2 1 note: all dimensions in millimeters . 48 fbga package marking scheme legend: xxxxxx= part number, s=speed, p=package llllll= lot code, yy=year, ww=work week examples: fm23mld16, ?green?/rohs fbga package, lot c8556953bg1, year 2008, work week 44 ramtron FM23MLD16-60-BG c8556953bg1 0844 ramtron xxxxxxx-s-p lllllll yyww
fm23mld16 - 512kx16 fram (multi die) rev. 2.0 june 2012 page 13 of 13 revision history revision date summary 1.0 12/12/2008 initial release. 1.1 1/4/2012 added esd ratings. 1.2 2/10/2012 changed timing parameters t as , t aap , and t dh . changed data retention table. 1.3 3/30/2012 changed package solder ball diameter. 2.0 6/27/2012 changed to production status.

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